1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to the programmable logic design software defining a synthesis algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to technology mapping, without degrading the power, speed or area of the design implementation.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The blocks of logic, often referred to by such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs), usually include one or more look up table (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions.
The programming software is used to develop a logic design that is to be implemented on the PLD device. The design flow of a typical programming software package generally includes design entry, synthesis, place and route, timing analysis, simulation and finally the configuration of the PLD device. A user will typically enter a logic design using a high level language such as Verilog or VHDL. Once the logic design has been entered, a gate level netlist is extracted from Verilog or VHDL. In the synthesis step, the netlist is broken down and implemented into the actual hardware resources available on the PLD device. The place and route module arranges the necessary hardware resource to implement the design on the device as efficiently as possible. Thereafter, the design is simulated and timing analysis is performed. Any modifications to the design to meet timing or performance specifications are typically identified and corrected at this stage. Once the design is finalized, the programming software next converts the output of the place and route module into a programming file. The programming contains the individual bits used to configure or program the hardware on the PLD to implement the intended logic design on the device.
The synthesis module of the programming software includes a number of modules. In a first stage called Register Transfer Language (RTL) or High Level Synthesis, the logic as defined by the gate level netlist is simplified. For example, a gate level netlist expression A+B+0 is simplified to A+B. In the next module called Multi Level Synthesis (MLS), the netlist defined by the High Level Synthesis module is reduced into an actual gate implementation using basic logic gates such as AND, OR, XOR, registers, etc. Finally, in a Technology Mapping (TM) step, the actual gate implementation as defined by the MLS module is mapped into the available hardware resources on the PLD, such as Look Up Tables, Logic Array Blocks, Memory Array Blocks, DSP blocks, etc. The output of the TM module is provided to the place and route module of the programming software.
There is a problem with the synthesis modules of currently known programming software packages. By the time the design is synthesized in the Technology Mapping stage, the power, area and maximum clock frequency (fmax) which the design can operate is predictable. If the power, area and/or fmax parameters for a given design are not acceptable or less than ideal, however, there is very little that can be done to remedy the problem. Generally speaking, the synthesis of the design at the Technology Mapping stage is too far along to implement any meaningful changes that would significantly impact or improve the power, area or fmax of the design.
Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs is therefore needed.